![]() ![]() It is one of the first steps after design entry and one of the last steps after implementation as part of the verifying the end functionality and performance of the design.įigure 1: Xilinx Simulation Flow Xilinx Simulation Libraries Overview Simulation can be applied at several points in the design flow ( Figure 1). ![]() ![]() UG626 Synthesis and Simulation Design Guide (ISE users) UG900 Vivado™ Design Suite Logic Simulation User’s Guide (Vivado users) This application note provides a quick overview of Xilinx®-targeted simulation flow based on Aldec’s design and verification environments, Active-HDL™ or Riviera-PRO™ detailed information can be found in the following Xilinx documents: Simulating a Design with Xilinx Libraries (UNISIM, UNIMACRO, XILINXCORELIB, SIMPRIMS, SECUREIP) ![]()
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